1. Field of the Invention
This disclosure relates generally to a semiconductor wafer and a processing method therefor, and more particularly relates to a semiconductor wafer having a groove structure in a passivation layer and a method for processing the same that can reduce damages to corners of cut-out dies.
2. Description of the Related Art
In semiconductor device manufacturing processes, after many steps such as deposition, photolithography and etching, a plurality of dies, which are separated from each other by scribe lane areas, are formed on a semiconductor wafer.
FIG. 1 is a schematic top view of a conventional semiconductor wafer. As shown in FIG. 1, a semiconductor wafer 100 comprises a plurality of dies 110 formed thereon in row and column directions, and the plurality of dies 110 are separated from each other by scribe lane areas 120. Although four dies 110 are shown in FIG. 1 as an example, the number of the dies 110 is not limited thereto.
Before cutting along the scribe lane areas 120 to singulate the plurality of dies 110 from each other, a passivation layer is generally formed on the plurality of dies 110 and the scribe lane areas 120 to protect the dies 110 and the like.
FIGS. 2A and 2B are schematic cross-sectional views of a conventional semiconductor wafer. As shown in FIGS. 2A and 2B, the semiconductor wafer may have an N well 205, a P well 210, a P+ region 215, an N+ region 220, inter-metal dielectric layers 225 and 235, metal layers 230 and 240, a top metal layer 250 and the like in a die area, for example. Furthermore, a passivation layer 260 is formed on the planarized top metal layer 250. Also, a pad window is usually formed in the passivation layer 260 to form a pad 265 (FIG. 2A) or 268 (FIG. 2B) therein. The difference between FIG. 2A and FIG. 2B lies in that, in FIG. 2A, the passivation layer 260 only comprises one passivation film, whereas in FIG. 2B, the passivation layer 260 comprises two passivation films 261 and 262, and a pad window is formed in each of the passivation films 261 and 262.
Thereafter, cutting is performed along the scribe lane areas 120 by using, for example, a rotating blade to singulate the plurality of dies 110 from each other (see FIG. 1).
The inventor of the present invention has conducted in-depth investigation on the above die sawing technique, and has found that the following problems exist: Due to the mechanical stress generated between the blade and the semiconductor wafer, chippings are likely to occur at die edges and cause cracks during the die-sawing process. This phenomenon is particularly pronounced at intersections of the scribe lane areas. Also, cracks at rough die edges are likely to propagate into the dies, thereby causing die deterioration or failure.